1. Field of the Invention
This invention relates to protective coating materials for semiconductor elements.
2. Description of the Prior Art
Heretofore, some prior art methods provide coating at least preselected exposed surface areas of semiconductor elements with electrically insulating oxide materials. Such coatings are thin layers and have virtually no resistance to mechanical abrasion and require relatively expensive processing equipment. In almost all instances a second and a thicker coat of a protective coating material is provided to protect the initial electrically insulating material. Silicone greases, varnishes, rubbers and resins which are employed as the overcoating of protective material have been found lacking in desirable physical characteristics.
Robert R. Shaw in U.S. Pat. No. 3,615,913, granted on Oct. 26, 1971, teaches the employment of a coating of a cured, protective coating material selected from the group consisting of polyimides, and polyamide-polyimides disposed on exposed end portions of at least one P-N junction to provide passivation thereof. Although these materials exhibited good abrasion resistance properties, the passivation requirements of the semiconductor element still required improvements to be made thereto.
There is currently wide spread use of oxide/glass layers for passivation and encapsulation of semiconductor devices where device stability and long life are important considerations. However, if the glassy layer must be applied after aluminum metallization, (a wide spread requirement), the choice of suitable glass systems is severely circumscribed by a maximum permissible application temperature of .about. 577.degree. C. This restriction is set by the alumina-silicon eutectic and must be carefully observed in all processing operations following aluminization of the silicon.
Several glass coating methods are currently in use. These include chemical vapor deposition (CVD), glass frits, and spin-on glass forming alcoholates. The last method is only capable of forming very thin layers, of the order of 2000A, of glasses which tend to be more reactive than desirable and, therefore, are of restricted utility in packaging. Glass frits are widely used in packaging but are not usually employed for surface passivation because of difficulties in formulating glasses with an adequate expansion match to silicon, and which are at the same time suitable passivants and chemically stable. CVD methods permit adequate thickness, a wide choice of composition, expansion matching, etc. but difficulties in controlling sodium contamination in CVD reactors have made it difficult to obtain acceptable passivation layers by direct deposition onto bare silicon. This method is, therefore, usually restricted to use as an overcoating of SiO.sub.2 and metallization layers. None of these methods in their current state of development is considered capable of providing a reliable passivation/encapsulation method for large thyristors and other power semiconductor devices.
The processing of such devices usually requires surface passivation of bare silicon p-n junctions with aluminum contacts already in place on the silicon. Thus the above-mentioned temperature restrictions on processing apply. Additionally, however, one must concern oneself with the surface charge of the passivation layer when it is directly applied to bare silicon. Such charge can be fixed and positive as in the case of a clean grown thermal oxide, or mobile, e.g., when due to the presence of sodium ion contamination of the oxide. Certain proprietary glass compositions give a negative fixed charge when applied to silicon.
Within limits, on some devices, an appropriate surface charge can be beneficial. For example, in the case of a P.sup.+N diode under reverse bias conditions, a negative surface charge will tend to deplete the surface of the n-type material, spread the depletion layer near the surface and hence lower surface electric field thus suppressing surface breakdown. On a P N+ diode, positive surface charge could have a similar beneficial effect if certain limits are not exceeded. Too much surface charge can cause surface inversion and channeling with a concommittant increase in surface leakage which is intolerable.
In many power devices, e.g., such as high voltage D.C. thyristors, the edges of the device are tapered or beveled in order to reduce surface fields and suppress surface breakdown. Since such devices are designed to block in both forward or reverse directions when not turned on by the control gate, one encounters the situation that on alternate half cycles maximum surface fields can exist on either side of lightly doped p-n junctions comprising the device and any surface charge will be deleterious favoring surface breakdown in either forward or reverse blocking conditions.
In such cases the most favorable surface coating is one which is charge neutral or nearly so. Currently, there are no known passivation coatings involving glasses or silicon oxides capable of giving such a desired charge neutral surface.
In the co-pending patent application it was my belief that a polyimide-silicone copolymer material, overlaid with a chemical vapor deposited glass layer was most desirable. However, it has been discovered that in some instances the silicone material need not be present.
Therefore, it is an object of this invention to provide a new and improved passivation process for semiconductor elements which overcomes the deficiencies of the prior art.
An object of this invention is to provide a semiconductor element having a passivation coating embodying at least one glass layer overcoating a polyimide polymer or a polyimide-silicone copolymer material layer.
Other objects of this invention will, in part, be obvious and will, in part, appear hereinafter.